1. Field of the Invention
The present invention generally relates to lithography in very large scale integrated (VLSI) chip manufacturing and, more particularly, to an improved phase shifted mask (PSM) lithography that enhances the lithographic window and improves resolution with a simpler and cheaper process.
2. Description of the Prior Art
A very large scale integrated (VLSI) complimentary metal oxide semiconductor (CMOS) chip is manufactured on a silicon wafer by a sequence of material additions (i.e., low pressure chemical vapor depositions, sputtering operations, etc.), material removals (i.e., wet etches, reactive ion etches, etc.), and material modifications (i.e., oxidations, ion implants, etc.). These physical and chemical operations interact with the entire wafer. For example, if a wafer is placed into an acid bath, the entire surface of the wafer will be etched away. In order to build very small electrically active devices on the wafer, the impact of these operations has to be confined to small, well defined regions.
Lithography in the context of VLSI manufacturing of CMOS devices is the process of patterning openings in photosensitive polymers (sometimes referred to as photoresists or resists) which define small areas in which the silicon base material is modified by a specific operation in a sequence of processing steps. The manufacturing of CMOS chips involves the repeated patterning of photoresist, followed by an etch, implant, deposition, or other operation, and ending in the removal of the expended photoresist to make way for a new resist to be applied for another iteration of this process sequence.
The basic lithography system consists of a light source, a stencil or photomask containing the pattern to be transferred to the wafer, a collection of lenses, and a means for aligning existing patterns on the wafer with patterns on the mask. Since a wafer containing from fifty to one hundred chips is patterned in steps of one to four chips at a time, these lithography tools are commonly referred to as steppers. The resolution of an optical projection system, such as a lithography stepper, is limited by the wavelength of the light used. State of the art steppers operate with deep ultra violet (DUV) light at 248 nanometer (nm) wavelength.
The photomask consists of chromium patterns on a quartz plate, allowing light to pass wherever the chromium is removed from the mask. The DUV light is projected through the mask onto the photoresist coated wafer, exposing the resist wherever hole patterns are placed on the mask. Exposing the resist to DUV light causes modifications in the molecular structure of the resist polymers which allows developer to dissolve and remove the resist in the exposed areas. (Negative resist systems allow only unexposed resist to be developed away.) The photomask, when illuminated, can be pictured as an array of individual, infinitely small light sources which can be either turned on (points in clear areas) or turned off (points covered by chrome). If the amplitude of the electric field vector which describes the light radiated by these individual light sources is mapped across a cross section of the mask, a step function will be plotted reflecting the two possible states that each point on the mask can be found in (light on, light off).
These conventional photomasks are commonly referred to as chrome on glass (COG) binary masks, due to the binary nature of the image amplitude. The perfectly square step function exists only in the theoretical limit of the exact mask plane. At any distance away from the mask, such as in the wafer plane, diffraction effects will cause images to exhibit a finite image slope. At small dimensions, that is, when the size and spacing of the images to be printed are small relative to the .lambda./NA (NA being the numerical aperture of the exposure system), electric field vectors of adjacent images will interact and add constructively. The resulting light intensity curve between the features is not completely dark, but exhibits significant amounts of light intensity created by the interaction of adjacent features. The resolution of an exposure system is limited by the contrast of the projected image, that is the intensity difference between adjacent light and dark features. An increase in the light intensity in nominally dark regions will eventually cause adjacent features to print as one combined structure rather than discrete images.
The quality with which small images can be replicated in lithography depends largely on the available process latitude; that is, the amount of allowable dose and focus variation that still results in correct image size. Phase shifted mask (PSM) lithography improves the lithographic process latitude by introducing a third parameter on the mask. The electric field vector defining the aerial image, like any vector quantity, has a magnitude and direction (expressed as the phase angle). PSMs capitalize on this vector property by modifying not only the magnitude of the transmitted electric field vector by blocking the light's path with chromium patters, but also the phase angle of the transmitted light at any transparent point on the mask. This phase variation is achieved in PSMs by modifying the length that a light beam travels through the mask material. By recessing the mask by the appropriate depth, light traversing the narrower portion of the mask and light traversing the wider portion of the mask will be 180.degree. out of phase; that is, their electric field vectors will be of equal magnitude but point in exactly opposite directions so that any interaction between these light beams results in perfect cancellation. For more information on PSM, the reader is referred to "Phase-Shifting Mask Stategies: Isolated Dark Lines", Marc D. Levenson, Microlithography World, March/April 1992, pp. 6-12.
The limits of PSM lithography can be uniquely challenged by the manufacture of high-performance advanced Dynamic Random Access Memory (DRAM) technologies and related logic circuitry. These technologies are entering development cycles with immediate requirements for sub-quarter micron printed gate lengths and tight dimensional control on the gate structures across large chip areas. Since these logic technologies are based on shrinking the gate length in an established DRAM technology, the overall layout pitch remains constant for all critical mask levels, resulting in narrow isolated lines on the scaled gate level. The requirement for tight line width control on narrow isolated lines drives the requirement of phase edge PSMs for these logic applications.
Phase edge PSM lithography makes use of contrast enhancement caused by a phase transition under an opaque feature on a mask. This phase transition is achieved by etching an appropriate depth into the quartz mask substrate on one side of a narrow line structure on the mask. Not all narrow line structures on the mask close upon themselves, some edges of the etched region will terminate in bare quartz regions. Since the 180.degree. phase transition forces a minimum in the image intensity, narrow dark lines will be printed by these excess phase edges. Currently, the unwanted images are erased using a trim mask.
The three major problems associated with phase edge lithography are design complexity, defect inspection and repair, and layout impacts driven by the required trim mask. While the design complexity and defect issues are common to most phase shifted mask technologies, the requirement for a trim mask and the associated layout constraints are unique to phase edge and alternating phase shifted masks. The fundamental problem with phase edge PSM, and a reason why many are not even considering this powerful technique, is the trade off between process latitude and integration density that has to be made due to the trim mask approach.